1. Field of the Invention
The present invention relates to a data processor which realizes a high processing ability by means of a sophisticated pipeline processing mechanism.
2. Description of Prior Art
Description is made on how to process an instruction performing a transfer from a register to a register, for example, by means of two kinds of instructions having different instruction formats in the data processor comprising the conventional pipeline mechanism.
FIG. 1 shows an example of a pipeline mechanism of a conventional data processor.
In FIG. 1, numeral 71 designates an instruction fetch (IF) stage, numeral 72 designates an instruction decoding (D) stage, numeral 73 designates an operand address calculation (A) stage, numeral 74 designates an operand fetch (F) stage and numeral 75 designates an instruction execution (E) stage.
The IF stage 71 fetches an instruction code from a memory (not shown) and outputs it to the D stage 72. The D stage 72 decodes the instruction code inputted from the IF stage 71 and outputs the decoding result to the A stage 73. The A stage 73 calculates an execute address of an operand specified in the instruction code and outputs the calculated operand address to the F stage 74. The F stage 74 fetches an operand from the memory according to the operand address inputted from the A stage 73 and accesses a micro-instruction from a micro-ROM (not shown) based on the decoding result, decodes this micro-instruction and outputs the decoding result to the E stage 75. The F stage 74 also outputs the fetched operand to the E stage 75. The E stage 75 executes an operation specified in the instruction code for the operand inputted from the F stage 74. Furthermore, it stores the operation result in a memory (not shown) as required.
Description is made on the case of processing, for example, two kinds of instructions whose instruction formats are shown in FIG. 2 and FIG. 3 respectively, that is, an A format instruction and a B format instruction by the conventional data processor as described above.
The A format instruction is an instruction between a memory and a register, and in the instruction code of this instruction, the memory designating field to become a destination and the register designating field to become a source are aligned in this sequence as shown in FIG. 2. On the other hand, the B format instruction is also an instruction between a memory and a register, but unlike the above-mentioned A format instruction, the memory designating field to become a source and the register designating field to become a destination are aligned in this sequence as shown in FIG. 3.
Hereinafter, description is made on the above-described two kinds of instructions, that is, the A format instruction and the B format instructions, for example, an instruction performing a transfer directly from a register to a register "MOV:A R1 R2" and "MOV:B R1 R2". Note that R1 and R2 specify a register 1 and a register 2 respectively.
This is the case of the instruction between a register and a memory wherein the memory becomes the register particularly. "MOV:A" means a transfer instruction of the A format and "MOV:B" means a transfer instruction of the B format respectively, and R1 specifies the register 1, and R2 specifies the register 2 respectively, and this assembly code means "MOV:? source destination" (here ? specifies A or B). The instruction "MOV:A R1 R2" becomes a code "0001 0010 00 **" in the instruction code and the instruction "MOV:B R1 R2" becomes a code "0010 0001 01 **" in the instruction code. Here, "0001" means the register 1, "0010" means the register 2, and the third field of two bits shows the A format or the B format, and the last field "**" specifies a MOV operation.
The above-described two kinds of instructions, the instruction "MOV:A R1 R2" and the "MOV:B R1 R2" are decoded independently, and in the F stage 74, according to the respective decoding results, the respective different microprograms are accessed and instructions are executed.
In the data processor having the conventional pipeline mechanism, in processing two kinds of instructions having different instruction formats, for example, the instruction "MOV:A R1 R2" and the instruction "MOV:B R1 R2", these instructions are decoded independently by a decoder and different decoding result are obtained. For this reason, different micro-programs are required to realize the substantially same function.